Field effect transistors (FET) include an active region, a gate electrode crossing over the active region, and source/drain electrodes formed adjacent the gate electrode. An active region under the gate electrode is used as a channel region that provides a moving path of charges (when the FET is turned on). With the high integration of semiconductor devices, the widths of the gate electrodes and active regions have become reduced. If, however, the width of the gate electrode is reduced, a length of the channel region (a space between a source region and a drain region) is also reduced. As a result, short channel effects (SCE), such as drain induced barrier lowering (DIBL) or punch-through, may occur. If the width of the active region is reduced, the width of the channel region (a length of a gate electrode in contact with the active region) may also be reduced, which may cause a narrow width effect that increases transistor threshold voltage.
The short channel effect and the narrow width effect occur because a voltage of the gate electrode controls an electronic state of the channel region incompletely. In order to completely control the electronic state of the channel region, a FinFET having a vertical channel region is suggested in U.S. Pat. No. 6,468,887. Since a gate electrode controls a channel region at three sides in this FinFET, it is possible to dramatically improve short channel effect and narrow width effect.
FIGS. 1 to 5 are cross-sectional views illustrating a method of fabricating the FinFET explained in U.S. Pat. No. 6,468,887. Referring to FIG. 1, a trench mask 3 is formed at a predetermined region of a semiconductor substrate 1. The semiconductor substrate 1 is anisotropically etched using the trench mask 3 as an etch mask. A fin-shaped active pattern 11 is formed under the trench mask pattern 3. Then, a sacrificial spacer 5 is formed on sidewalls of the active pattern 11.
An insulating layer is formed on a resultant structure where the sacrificial spacer 5 is formed. The insulating layer is planarizingly etched until the trench mask 3 and the sacrificial spacer 5 are exposed. Accordingly, a device isolation layer 23 filling a space between the active patterns 11 is formed. After that, the exposed trench mask 3 and the sacrificial spacer 5 are removed to form an opening 6. As illustrated by FIG. 2, the opening 6 exposes a lower surface (an upper surface of the semiconductor substrate 1) of the trench 2 between the device isolation layer 23 and the active pattern 11. Referring now to FIG. 3, a gate insulating layer 12 is formed on a surface of the active pattern 11 exposed by the opening 6. A gate conductive layer filled in the opening 6 is formed on the above resultant structure. Continuously, the gate conductive layer is patterned to form a gate electrode crossing over the active pattern 11.
After forming the gate electrode 22, impurity regions 24 are formed by performing an ion implantation process using the gate electrode 22 and the device isolation layer 23 as a mask. FIGS. 4 and 5 are cross-sectional views that show a resultant structure where the impurity region 24 is formed in the vertical direction with respect to FIG. 3 and show sections at a position of the active pattern (I) 11 and the opening (II) 6.
In accordance with U.S. Pat. No. 6,468,887, the opening 6 forms a closed curve exposing a lower surface of the trench 2 at the edge of the active pattern 11. In order to form the gate electrode 22 without a bridge, the gate conductive layer should be etched until the lower surface of the trench 2. However, now that the gate conductive layer has a significant thickness difference, it is difficult to pattern the gate conductive layer without etching damage. In other words, since a thickness h1 of the gate conductive layer filled in the opening 6 is still thicker than a thickness h2 of the gate conductive layer stacked on the active pattern 11, it is difficult for the gate conductive layer to be completely etched in the opening 6 without causing etching damage with respect to the active pattern 11. In particular, a feasibility of the above-mentioned etching process for forming the gate electrode 22 is little in that the gate conductive layer and the active pattern 11 are formed of silicon.
Furthermore, in accordance with U.S. Pat. No. 6,468,887, since a part of the opening 6 (a region is not covered with the gate electrode 22) is exposed during an ion implantation process for forming the impurity region 24; parasitic impurity regions 24′ may be formed under the opening 6. In this case, as shown in FIG. 5, the parasitic impurity regions 24′ are constituted by a parasitic transistor together with the gate electrode 22 and the gate insulating layer 12.